1. Field of the Invention
The invention relates in general to a current-mode sense amplifier and sense amplifying method, and more particularly to a low-power current-mode sense amplifier and sense amplifying method suitable for flash memory.
2. Description of the Related Art
FIG. 1A is a block diagram of a conventional current-mode sense amplifier applied in a flash memory. As shown in FIG. 1A, a conventional current-mode sense amplifier 100 includes a first current mirror 102, a second current mirror 104, an amplifying circuit 106 and an output stage circuit 108. The first current mirror 102 is for outputting a cell current Icell to a memory cell 110 and generating a mirrored cell current Icell′ according to the cell current Icell, while the second current mirror 104 is for outputting a reference current Iref to a reference cell 120 and generating a mirrored reference current Iref′ according to the reference current Iref.
Moreover, the amplifying circuit 106 is coupled to the first current mirror 102 and the second current mirror 104 for receiving the mirrored cell current Icell′ and receiving the mirrored reference current Iref′. The output stage circuit 108 is coupled to the amplifying circuit 106 for outputting an output signal OUT.
FIG. 1B is a conventional circuit diagram of the amplifying circuit 106 of FIG. 1A. As shown in FIG. 1B, the amplifying circuit 106 includes P-type metal oxide semiconductor (PMOS) transistors P1 and P2, and N-type metal oxide semiconductor (NMOS) transistors N1˜N6. The transistors P1, N1 and N2 are coupled in series and the transistors P1, N1 and N2 are coupled in series between the voltage VDD and a drain of the transistor N6. The source of the transistor N1 is for receiving the mirrored cell current Icell′ and the source of the transistor N3 is for receiving the mirrored reference current Iref′. The transistor N5 is coupled between the transistors N1 and N3, and controlled by a first clock CLK1. The transistor N6 is controlled by a second clock CLK2.
Conventionally, as shown in FIG. 1C, in a charging period t1, the transistors N5 and N6 are respectively turned on by the clocks CLK1 and CLK2, both having a high level. The memory cell 110 and the reference cell 120 are respectively charged by large cell and reference currents Icell and Iref (charging currents), meanwhile a large mirrored cell current Icell′ is generated to flow through the transistors N2 and N6 to the ground voltage GND and a large mirrored reference current Iref′ is generated to flow through the transistors N4 and N6 to GND. Then, in the period t2, the transistor N5 is turned off by the first clock CLK1 and the transistor N2 maintains turned on by the second clock CLK2. The drain voltages V1 and V3 of the transistors N1 and N3 are adjusted to the voltage VDD or GND according to a current I2 flowing by the transistor N2 corresponding to the stable current Icell′ and a current I4 flowing by the transistor N4 corresponding to the stable current Iref′ as shown in FIG. 1B. Finally, the output stage circuit 108 outputs the signal OUT (1/0) according to the adjusted voltages V1 and V3.
However, the conventional current-mode sense amplifier has the following advantages:
(1) Large charging currents respectively flowing through the transistors N2, N6 and N4, N6 to GND in the charging period t1 lead to extra current (or power) consumption before the period t2 is reached when the mirrored cell current Icell′ and mirrored reference current Iref′ are stable enough. A great amount of power will be wasted as a large number of sense amplifiers are used in the flash memory.
(2) Due to MOSFET mismatch between transistors P1, N1, N2 and P2, N3, N4, the above-mentioned currents I2 and I4, such as 10 uA to 100 uA, may have an error current about tenth of the currents I2 and I4, such as 1 uA to 10 uA. The larger the operational voltage VDD (2.5V˜3.7V) is, the larger the error current becomes. Therefore, the conventional current-mode amplifier 100 must maintain large current difference between Icell and Iref to combat with the error current generated from MOSFET offset. As the flash memory is designed to be smaller, the current difference between Icell and Iref becomes smaller. As soon as the error current is larger than the current difference between Icell and Iref, the current-mode sense amplifier 100 will malfunction.